数字IC设计实操

一、Design Compiler综合

综合,在终端下输入dc

dv_use_pref_reader_version 1 {
# Design Vision version K-2015.06
# Preferences written on Sat Apr 1 19:39:54 2017
gui_set_var -name {read_pref_file} -value {true}
gui_create_pref_key -category {Globals} -key {allow_source_line_highlighting} -value_type {bool} -value {true}
gui_create_pref_key -category {Globals} -key {enable_cross_probe_from_rtl} -value_type {bool} -value {true}
gui_create_pref_key -category {Globals} -key {enable_rtl_source_view_in_congestion} -value_type {bool} -value {true}
gui_create_pref_key -category {Globals} -key {rtl_grouping_style} -value_type {string} -value {FileName-LineNumber Grouping}
gui_set_var -name {read_pref_file} -value {false}
}

一般.synopsys_dc.setup 文件有三个:①一个在synopsys的安装目录下,这个文件最好不要动;②一个在用户目录下,这个文件没事也不要动他;③还有一个当前工作目录下,也就是启动DC的目录下(没有就需要自己创建),这个是要我们自己写的,这个想怎么动就怎么动。我们配置DC的启动环境,就是在启动的目录创建.synopsys_dc.setup并且修改它。

这里,我们直接读入设计文件Adder16.v。

module Adder16 (ain, bin, cin, sout, cout, clk);
/* Sixteen Bit Adder Module */
output [15:0] sout;
output cout;
input [15:0] ain, bin;
input cin, clk;
 
wire [15:0] sout_tmp, ain, bin;
wire cout_tmp;
reg [15:0] sout, ain_tmp, bin_tmp;
reg cout, cin_tmp;
 
always @(posedge clk) begin
   cout = cout_tmp;
   sout = sout_tmp;
   ain_tmp = ain;
   bin_tmp = bin;
   cin_tmp = cin;
end
   assign {cout_tmp,sout_tmp} = ain_tmp + bin_tmp + cin_tmp;
endmodule
dc_shell> read_file Adder16.v
Information: Inferring file format verilog based on file name extension(s). (UID-1034)
Loading db file '/opt/Foundary_Library/TSMC90/aci/sc-x/synopsys/fast.db'
Loading db file '/opt/Foundary_Library/TSMC90/aci/sc-x/synopsys/fast_leakage.db'
Loading db file '/opt/Foundary_Library/TSMC90/aci/sc-x/synopsys/fastz.db'
Loading db file '/opt/Foundary_Library/TSMC90/aci/sc-x/synopsys/slow.db'
Loading db file '/opt/Foundary_Library/TSMC90/aci/sc-x/synopsys/typical.db'
Loading db file '/opt/Foundary_Library/TSMC90/aci/sc-x/synopsys/typical_leakage.db'
Loading db file '/opt/Synopsys/Synplify2015/libraries/syn/gtech.db'
Loading db file '/opt/Synopsys/Synplify2015/libraries/syn/standard.sldb'
  Loading link library 'fast'
  Loading link library 'fast_leakage'
  Loading link library 'fastz'
  Loading link library 'slow'
  Loading link library 'typical'
  Loading link library 'typical_leakage'
  Loading link library 'gtech'
Loading verilog file '/home/IC/Documents/synplify/dw01/adder16/Adder16.v'
Detecting input file type automatically (-rtl or -netlist).
Reading with Presto HDL Compiler (equivalent to -rtl option).
Running PRESTO HDLC
Compiling source file /home/IC/Documents/synplify/dw01/adder16/Adder16.v

Inferred memory devices in process
	in routine Adder16 line 13 in file
		'/home/IC/Documents/synplify/dw01/adder16/Adder16.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      cout_reg       | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|      sout_reg       | Flip-flop |  16   |  Y  | N  | N  | N  | N  | N  | N  |
|     ain_tmp_reg     | Flip-flop |  16   |  Y  | N  | N  | N  | N  | N  | N  |
|     bin_tmp_reg     | Flip-flop |  16   |  Y  | N  | N  | N  | N  | N  | N  |
|     cin_tmp_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================
Presto compilation completed successfully.
Current design is now '/home/IC/Documents/synplify/dw01/adder16/Adder16.db:Adder16'
Loaded 1 design.
Current design is 'Adder16'.
Adder16

如果我们使用tcl文件,直接运行命令:

source adder16.tcl

set design "adder16"
current_design Adder16
# Define design environment 
set_load 2.2 sout
set_load 1.5 cout


# Define design constraints 
set_input_delay 1.35 -clock $clk_name {ain bin}
set_input_delay 3.5 -clock $clk_name cin
set_max_area 0

compile
write_file -format ddc -hierarchy -output adder16.ddc
write -f verilog -hierarchy -output adder16.v
write_sdc adder16.sdc

运行结果:

dc_shell> source adder16.tcl
Current design is 'Adder16'.

Information: There are 6 potential problems in your design. Please run 'check_design' for more information. (LINT-99)


Warning: Operating condition fast set on design Adder16 has different process,
voltage and temperatures parameters than the parameters at which target library 
fast_leakage is characterized. Delays may be inaccurate as a result. (OPT-998)

  Beginning Pass 1 Mapping
  ------------------------
  Processing 'Adder16_DW01_add_0'
  Processing 'Adder16'

  Updating timing information
Information: Updating design information... (UID-85)

  Beginning Implementation Selection
  ----------------------------------

  Beginning Mapping Optimizations  (Medium effort)
  -------------------------------

                                  TOTAL                                      
   ELAPSED            WORST NEG   SETUP    DESIGN                            
    TIME      AREA      SLACK     COST    RULE COST         ENDPOINT         
  --------- --------- --------- --------- --------- -------------------------
    0:00:01    1875.5      0.00       0.0      55.7                          
    0:00:01    1875.5      0.00       0.0      55.7                          
    0:00:01    1875.5      0.00       0.0      55.7                          
    0:00:01    1875.5      0.00       0.0      55.7                          
    0:00:01    1875.5      0.00       0.0      55.7                          
    0:00:01    1120.5      0.00       0.0      55.7                          
    0:00:01    1120.5      0.00       0.0      55.7                          
    0:00:01    1120.5      0.00       0.0      55.7                          
    0:00:01    1120.5      0.00       0.0      55.7                          
    0:00:01    1120.5      0.00       0.0      55.7                          
    0:00:01    1289.8      0.00       0.0       2.2                          
    0:00:02    1298.3      0.00       0.0       0.2                          
    0:00:02    1298.3      0.00       0.0       0.2                          
    0:00:02    1298.3      0.00       0.0       0.2                          
    0:00:02    1298.3      0.00       0.0       0.2                          



  Beginning Delay Optimization Phase
  ----------------------------------

                                  TOTAL                                      
   ELAPSED            WORST NEG   SETUP    DESIGN                            
    TIME      AREA      SLACK     COST    RULE COST         ENDPOINT         
  --------- --------- --------- --------- --------- -------------------------
    0:00:02    1298.3      0.00       0.0       0.2                          
    0:00:02    1298.3      0.00       0.0       0.2                          
    0:00:02    1298.3      0.00       0.0       0.2                          


  Beginning Design Rule Fixing  (max_capacitance)
  ----------------------------

                                  TOTAL                                      
   ELAPSED            WORST NEG   SETUP    DESIGN                            
    TIME      AREA      SLACK     COST    RULE COST         ENDPOINT         
  --------- --------- --------- --------- --------- -------------------------
    0:00:02    1298.3      0.00       0.0       0.2                          


  Beginning Area-Recovery Phase  (max_area 0)
  -----------------------------

                                  TOTAL                                      
   ELAPSED            WORST NEG   SETUP    DESIGN                            
    TIME      AREA      SLACK     COST    RULE COST         ENDPOINT         
  --------- --------- --------- --------- --------- -------------------------
    0:00:02    1298.3      0.00       0.0       0.2                          
    0:00:02    1298.3      0.00       0.0       0.2                          
    0:00:02    1298.3      0.00       0.0       0.2                          
    0:00:02    1298.3      0.00       0.0       0.2                          
    0:00:02    1298.3      0.00       0.0       0.2                          
    0:00:02    1298.3      0.00       0.0       0.2                          
    0:00:02    1286.3      0.00       0.0       0.2                          
    0:00:02    1286.3      0.00       0.0       0.2                          
    0:00:02    1286.3      0.00       0.0       0.2                          
    0:00:02    1286.3      0.00       0.0       0.2                          
    0:00:02    1286.3      0.00       0.0       0.2                          
    0:00:02    1286.3      0.00       0.0       0.2                          
    0:00:02    1286.3      0.00       0.0       0.2                          
    0:00:02    1286.3      0.00       0.0       0.2                          
    0:00:02    1286.3      0.00       0.0       0.2                          
    0:00:02    1286.3      0.00       0.0       0.2                          
    0:00:02    1286.3      0.00       0.0       0.2                          
    0:00:02    1286.3      0.00       0.0       0.2                          
Loading db file '/opt/Foundary_Library/TSMC90/aci/sc-x/synopsys/fast.db'
Loading db file '/opt/Foundary_Library/TSMC90/aci/sc-x/synopsys/fastz.db'
Loading db file '/opt/Foundary_Library/TSMC90/aci/sc-x/synopsys/slow.db'
Loading db file '/opt/Foundary_Library/TSMC90/aci/sc-x/synopsys/typical.db'


Note: Symbol # after min delay cost means estimated hold TNS across all active scenarios 


  Optimization Complete
  ---------------------
Writing ddc file 'adder16.ddc'.

输出的文件

一个是生成.ddc文件,里面包含了很多信息。一个是生成.v的门级网表。一个是生成标准约束文件,以供后面进行布局布线提供参考。

二、ICC布局布线

在终端启动icc_shell -gui

接着点击File->Create Library

创建完Library之后导入Design

读入设计后,进入Layout窗口

进入Layout Window后创建Floorplan。

创建完Floorplan之后,进入ICC主窗口create_fp_placement

随时保存一下,File->Save Design。

接着,进行自动布线:

自动布线之后的结果

写入GDSII文件File->Export->Write Stream

将gds文件导入L-edit中查看

发现连线导出了,但是用到的cell没有出来

时钟树综合(CTS),命令是clock_opt。也可以在图形界面选择Clock->Core CTS and Optimization。

这里需要注意一点,如果你的tf文件中没有capacitance这一项,就会报错:

我们在tf文件中加上下面红字的三行,重新建立Library,导入Design,进行floorplan和CTS。

Layer		"M1" {
		layerNumber			= 31
		maskName			= "metal1"
		isDefaultLayer			= 1
		visible				= 1
		selectable			= 1
		blink				= 0
		color				= "cyan"
		lineStyle			= "solid"
		pattern				= "dot"
		pitch				= 0.28
		defaultWidth			= 0.12
		minWidth			= 0.12
		minSpacing			= 0.12
		maxWidth			= 12
		maxCurrDensity			= 20
		unitMinCapacitance		= 3.89e-05
		unitNomCapacitance		= 4.22e-05
		unitMaxCapacitance		= 4.61e-05
		unitMinResistance		= 0.00013
		unitNomResistance		= 0.00013
		unitMaxResistance		= 0.00013
		fatTblDimension			= 4
		fatTblThreshold			= (0,0.305,1.505,4.505)
		fatTblParallelLength		= (0,0.525,1.505,4.505)
		fatTblSpacing			= (0.12,0.17,0.5,1.5,
						   0.17,0.17,0.5,1.5,
						   0.5,0.5,0.5,1.5,
						   1.5,1.5,1.5,1.5)
		minArea				= 0.058
		minEnclosedArea			= 0.2
}

就会看到CTS Successful:

这里列出所有控制台输出:

icc_shell> clock_opt
Warning: Starting from the 2011.09-SP4 release, clock_opt will NOT perform congestion-driven placement by default. (PSYN-1111)

The options for clock_opt:
--------------------------
COPT:  Clock Tree Synthesis                 : Yes
COPT:  Post CTS Optimization                : Yes
COPT:  Concurrent Clock/Data Optimization   : No
COPT:  Operation Condition                  : max
COPT:  Balance Inter Clock Delay            : No
COPT:  Route Clock Nets                     : Yes
COPT:  Update Clock Latency                 : No
COPT:  Optimize Hold for All Clocks         : No
COPT:  Optimize Hold Timing Only            : No
COPT:  Optimize DFT                         : No
COPT:  Area Recovery                        : No
COPT:  Size Only                            : No
COPT:  In Place Size Only                   : No
COPT:  Congestion removal                   : No
COPT:  Optimize Power                       : No
---------------------------------------------------

Executing ICC clock_opt...
medium
*
Building clock tree...
Operating Condition is max
Information: There is no scenario with cts_mode set to true, CTS will use old cts_scenario flow. (CTS-1115)
CTS: CTS Operating Condition(s): MAX(Worst) 

  Loading design 'Adder16'
Warning: Layer 'M1' is missing the optional 'edge capacitance' attribute. (PSYN-101)
Warning: Layer 'M2' is missing the optional 'edge capacitance' attribute. (PSYN-101)
Warning: Layer 'M3' is missing the optional 'edge capacitance' attribute. (PSYN-101)
Warning: Layer 'M4' is missing the optional 'edge capacitance' attribute. (PSYN-101)
Warning: Layer 'M5' is missing the optional 'edge capacitance' attribute. (PSYN-101)
Warning: Layer 'M6' is missing the optional 'edge capacitance' attribute. (PSYN-101)
Warning: Layer 'M7' is missing the optional 'edge capacitance' attribute. (PSYN-101)
Warning: Layer 'M8' is missing the optional 'edge capacitance' attribute. (PSYN-101)
Warning: Layer 'M9' is missing the optional 'edge capacitance' attribute. (PSYN-101)




Information: Library Manufacturing Grid(GridResolution) : 5
Information: Time Unit from Milkyway design library: 'ns' 
Information: Design Library and main library timing units are matched - 1.000 ns. 
Information: Resistance Unit from Milkyway design library: 'kohm' 
Information: Design Library and main library resistance units are matched - 1.000 kohm. 
Information: Capacitance Unit from Milkyway design library: 'pf' 
Information: Design Library and main library capacitance units are matched - 1.000 pf. 
[begin initializing data for legality checker]

Initializing Data Structure ...
INFO: legalizer_via_spacing_check_mode 0
  Reading technology information ...
    Technology table contains 9 routable metal layers
    This is considered as a 9-metal-layer design
    Reading library information from DB ...
  Reading misc information ...
    array <unit> has 0 vertical and 17 horizontal rows
    GRC ref loc X corrected
    GRC ref loc Y corrected
  Checking information read in ...
    design style = Horizontal masters, Horizontal rows

  Preprocessing design ...
    splitting rows by natural obstacles ...
... design style 0
... number of base array 1 0
INFO:... use original rows...
[end initializing data for legality checker]
Setting the GR Options
Information: The distance unit in Capacitance and Resistance is 1 micron. (RCEX-007)
Information: The RC model used is library 1D. (RCEX-015)
Information: Library Derived Cap for layer M1 : 5.1e-06 5.1e-06 (RCEX-011)
Information: Library Derived Res for layer M1 : 0.0011 0.0011 (RCEX-011)
Information: Library Derived Cap for layer M2 : 5.9e-06 5.9e-06 (RCEX-011)
Information: Library Derived Res for layer M2 : 0.00058 0.00058 (RCEX-011)
Information: Library Derived Cap for layer M3 : 5.9e-06 5.9e-06 (RCEX-011)
Information: Library Derived Res for layer M3 : 0.00058 0.00058 (RCEX-011)
Information: Library Derived Cap for layer M4 : 5.9e-06 5.9e-06 (RCEX-011)
Information: Library Derived Res for layer M4 : 0.00058 0.00058 (RCEX-011)
Information: Library Derived Cap for layer M5 : 5.9e-06 5.9e-06 (RCEX-011)
Information: Library Derived Res for layer M5 : 0.00058 0.00058 (RCEX-011)
Information: Library Derived Cap for layer M6 : 5.9e-06 5.9e-06 (RCEX-011)
Information: Library Derived Res for layer M6 : 0.00058 0.00058 (RCEX-011)
Information: Library Derived Cap for layer M7 : 5.9e-06 5.9e-06 (RCEX-011)
Information: Library Derived Res for layer M7 : 0.00058 0.00058 (RCEX-011)
Information: Library Derived Cap for layer M8 : 1.8e-05 1.8e-05 (RCEX-011)
Information: Library Derived Res for layer M8 : 6.5e-05 6.5e-05 (RCEX-011)
Information: Library Derived Cap for layer M9 : 1.8e-05 1.8e-05 (RCEX-011)
Information: Library Derived Res for layer M9 : 6.5e-05 6.5e-05 (RCEX-011)
Information: Library Derived Horizontal Cap : 8.1e-06 8.1e-06 (RCEX-011)
Information: Library Derived Horizontal Res : 0.00058 0.00058 (RCEX-011)
Information: Library Derived Vertical Cap : 8.9e-06 8.9e-06 (RCEX-011)
Information: Library Derived Vertical Res : 0.00045 0.00045 (RCEX-011)
Information: Using derived R and C coefficients. (RCEX-008)
Information: Using region-based R and C coefficients. (RCEX-013)
Information: Library Derived Via Res : 0.002 0.002 (RCEX-011)
LR: Layer M3: Average tracks per gcell 9.0, utilization 0.00
LR: Layer M4: Average tracks per gcell 9.0, utilization 0.00
LR: Layer M5: Average tracks per gcell 9.0, utilization 0.00
LR: Layer M6: Average tracks per gcell 9.0, utilization 0.00
LR: Layer M7: Average tracks per gcell 9.0, utilization 0.00
LR: Layer M8: Average tracks per gcell 2.9, utilization 0.00
LR: Layer M9: Average tracks per gcell 2.9, utilization 0.00
LR: Clock routing service standing by
Using cts integrated global router
CTS: Blockage Aware Algorithm
CTS: Top-Level OCV Path Sharing not effective when timing derating is too low
[begin initializing data for legality checker]

Initializing Data Structure ...
INFO: legalizer_via_spacing_check_mode 0
  Reading technology information ...
    Technology table contains 9 routable metal layers
    This is considered as a 9-metal-layer design
    Reading library information from DB ...
  Reading misc information ...
    array <unit> has 0 vertical and 17 horizontal rows
    GRC ref loc X corrected
    GRC ref loc Y corrected
  Checking information read in ...
    design style = Horizontal masters, Horizontal rows

  Preprocessing design ...
    splitting rows by natural obstacles ...
... design style 0
... number of base array 1 0
INFO:... use original rows...
[end initializing data for legality checker]
CTS: Region Aware Algorithm is automatically turned off when design has no region or only has one region.
CTS-Warning: clock root not found
CTS: ==================================================
CTS: Start DRC fixing beyond exceptions
CTS: Blockage Aware Algorithm
CTS: Top-Level OCV Path Sharing not effective when timing derating is too low
[begin initializing data for legality checker]

Initializing Data Structure ...
INFO: legalizer_via_spacing_check_mode 0
  Reading technology information ...
    Technology table contains 9 routable metal layers
    This is considered as a 9-metal-layer design
    Reading library information from DB ...
  Reading misc information ...
    array <unit> has 0 vertical and 17 horizontal rows
    GRC ref loc X corrected
    GRC ref loc Y corrected
  Checking information read in ...
    design style = Horizontal masters, Horizontal rows

  Preprocessing design ...
    splitting rows by natural obstacles ...
... design style 0
... number of base array 1 0
INFO:... use original rows...
[end initializing data for legality checker]
CTS: Region Aware Algorithm is automatically turned off when design has no region or only has one region.
CTS-Warning: clock root not found
CTS: DRC fixing initialization error. Abort
CTS: ==================================================
Information: The distance unit in Capacitance and Resistance is 1 micron. (RCEX-007)
Information: The RC model used is library 1D. (RCEX-015)
Information: Library Derived Cap for layer M1 : 5.1e-06 5.1e-06 (RCEX-011)
Information: Library Derived Res for layer M1 : 0.0011 0.0011 (RCEX-011)
Information: Library Derived Cap for layer M2 : 5.9e-06 5.9e-06 (RCEX-011)
Information: Library Derived Res for layer M2 : 0.00058 0.00058 (RCEX-011)
Information: Library Derived Cap for layer M3 : 5.9e-06 5.9e-06 (RCEX-011)
Information: Library Derived Res for layer M3 : 0.00058 0.00058 (RCEX-011)
Information: Library Derived Cap for layer M4 : 5.9e-06 5.9e-06 (RCEX-011)
Information: Library Derived Res for layer M4 : 0.00058 0.00058 (RCEX-011)
Information: Library Derived Cap for layer M5 : 5.9e-06 5.9e-06 (RCEX-011)
Information: Library Derived Res for layer M5 : 0.00058 0.00058 (RCEX-011)
Information: Library Derived Cap for layer M6 : 5.9e-06 5.9e-06 (RCEX-011)
Information: Library Derived Res for layer M6 : 0.00058 0.00058 (RCEX-011)
Information: Library Derived Cap for layer M7 : 5.9e-06 5.9e-06 (RCEX-011)
Information: Library Derived Res for layer M7 : 0.00058 0.00058 (RCEX-011)
Information: Library Derived Cap for layer M8 : 1.8e-05 1.8e-05 (RCEX-011)
Information: Library Derived Res for layer M8 : 6.5e-05 6.5e-05 (RCEX-011)
Information: Library Derived Cap for layer M9 : 1.8e-05 1.8e-05 (RCEX-011)
Information: Library Derived Res for layer M9 : 6.5e-05 6.5e-05 (RCEX-011)
Information: Library Derived Horizontal Cap : 8.1e-06 8.1e-06 (RCEX-011)
Information: Library Derived Horizontal Res : 0.00058 0.00058 (RCEX-011)
Information: Library Derived Vertical Cap : 8.9e-06 8.9e-06 (RCEX-011)
Information: Library Derived Vertical Res : 0.00045 0.00045 (RCEX-011)
Information: Using derived R and C coefficients. (RCEX-008)
Information: Using region-based R and C coefficients. (RCEX-013)
Information: Library Derived Via Res : 0.002 0.002 (RCEX-011)
 CTS Successful 
Optimizing clock tree...
Operating Condition is max
No valid clocks specified, all clocks will be optimized
CTS: CTS Operating Condition(s): MAX(Worst) 
enable delay detour in ctdn

  Legalizing Placement
  --------------------

[begin initializing data for legality checker]

Initializing Data Structure ...
INFO: legalizer_via_spacing_check_mode 0
  Reading technology information ...
    Technology table contains 9 routable metal layers
    This is considered as a 9-metal-layer design
    Reading library information from DB ...
  Reading misc information ...
    array <unit> has 0 vertical and 17 horizontal rows
    GRC ref loc X corrected
    GRC ref loc Y corrected
  Checking information read in ...
    design style = Horizontal masters, Horizontal rows

  Preprocessing design ...
    splitting rows by natural obstacles ...
... design style 0
... number of base array 1 0
INFO:... use original rows...
[end initializing data for legality checker]
 
****************************************
  Report : Chip Summary
  Design : Adder16
  Version: L-2016.03-SP1
  Date   : Sun Jun  5 01:58:50 2022
****************************************
Std cell utilization: 70.09%  (1823/(2601-0))
(Non-fixed + Fixed)
Std cell utilization: 70.09%  (1823/(2601-0))
(Non-fixed only)
Chip area:            2601     sites, bbox (0.00 0.00 42.84 42.84) um
Std cell area:        1823     sites, (non-fixed:1823   fixed:0)
                      100      cells, (non-fixed:100    fixed:0)
Macro cell area:      0        sites
                      0        cells
Placement blockages:  0        sites, (excluding fixed std cells)
                      0        sites, (include fixed std cells & chimney area)
                      0        sites, (complete p/g net blockages)
Routing blockages:    0        sites, (partial p/g net blockages)
                      0        sites, (routing blockages and signal pre-route)
Lib cell count:       5 
Avg. std cell width:  5.26 um 
Site array:           unit     (width: 0.28 um, height: 2.52 um, rows: 17)
Physical DB scale:    1000 db_unit = 1 um 

 
****************************************
  Report : pnet options
  Design : Adder16
  Version: L-2016.03-SP1
  Date   : Sun Jun  5 01:58:50 2022
****************************************


--------------------------------------------------------------------
Layer      Blockage   Min_width   Min_height   Via_additive     Density
--------------------------------------------------------------------
M1         none          ---         ---       via additive      ---
M2         none          ---         ---       via additive      ---
M3         none          ---         ---       via additive      ---
M4         none          ---         ---       via additive      ---
M5         none          ---         ---       via additive      ---
M6         none          ---         ---       via additive      ---
M7         none          ---         ---       via additive      ---
M8         none          ---         ---       via additive      ---
M9         none          ---         ---       via additive      ---
 
****************************************
  Report : Legalize Displacement
  Design : Adder16
  Version: L-2016.03-SP1
  Date   : Sun Jun  5 01:58:50 2022
****************************************

No cell displacement.


  Placement Legalization Complete
  -------------------------------

Information: Updating database...
Unsetting the GR Options
LR: 0 out of 0 clock nets rerouted
LR: Clock routing service terminated
Invalidate design extracted status
Optimize clock tree UnSuccessful... Aborting clock_opt
0

时钟树综合之后,可以使用report_timing命令来看报告:

三、Milkyway的使用

Milkway图形界面启动


Milkyway  -galaxy  -tcl

物理库:描述了工艺层次,工艺规则以及标准单元等IP的形状大小,端口位置信息,目前业内标准是(.lef)格式,但是Synopsys的ICC使用Milkway格式的数据库,其中的fram view就是物理库,其本质和lef一样,ICC2放弃了Milkyway,使用(.db)和(.lef)生成的ndm作为参考库创建ndb。通常情况下,IO单元和标准单元的Milkyway库由IP提供商提供,而宏单元(Macro)的Milkway需要后端设计人员用Synopsys专门的EDA工具Milkyway根据宏单元的GDS文件或lef文件生成。
对于每一个工艺的参考库,都有专门的技术文件(Technology File)来说明其工艺的参数信息,技术文件简称(.tf)文件,产生Milkyway物理库和ndb时需要用到此文件。
技术文件通常由工艺厂提供,文件主要包含了每层掩膜层的层号,连接层信息,子啊EDA工具中显示的颜色与线条,最小宽度,最小面积等信息。ICC就是根基技术文件中的描述的金属层和通孔层的设计规则进行布局布线的。

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