使用Quartus进行数字电路设计时，遇到了下面的编译错误：
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 11.0 Build 157 04/27/2011 SJ Full Version
Info: Processing started: Thu May 15 13:09:59 2014
Info: Command: quartus_map –read_settings_files=on –write_settings_files=off simulate -c simulate
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Found 1 design units, including 1 entities, in source file simulate.v
Info: Found entity 1: modelsim_test
Error: Top-level design entity “simulate” is undefined
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 324 megabytes
Error: Processing ended: Thu May 15 13:10:01 2014
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings
原因是
verilog文件（.v）里的模块名和顶层实体名(Top-level design entity，一般就是.v文件的文件名)不一致。
module modelsim_test(clk,rst_n,div);
input clk;
input rst_n;
output div;
reg div;
always@(posedge clk or negedge rst_n)
if(!rst_n)div<=1'b0;
else div<=~div;
endmodule 上面的模块名是modelsim_test，而工程目录下的verilog文件名是simulate，如下图。
解决方法是：将modelsim_test修改为simulate。
编译成功！