QuartusII软件异常:Error: Top-level design entity ” ” is undefined


Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
 Info: Version 11.0 Build 157 04/27/2011 SJ Full Version
 Info: Processing started: Thu May 15 13:09:59 2014
Info: Command: quartus_map –read_settings_files=on –write_settings_files=off simulate -c simulate
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Found 1 design units, including 1 entities, in source file simulate.v
 Info: Found entity 1: modelsim_test
Error: Top-level design entity “simulate” is undefined

Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
 Error: Peak virtual memory: 324 megabytes
 Error: Processing ended: Thu May 15 13:10:01 2014
 Error: Elapsed time: 00:00:02
 Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings


verilog文件(.v)里的模块名和顶层实体名(Top-level design entity,一般就是.v文件的文件名)不一致。